S1C33A01 cmos 32-bit application specific controller z 32-bit risc cpu core (epson s1c33 pe core) (max. 90 mhz operation) z 1kb instruction cache and 1kb data cache z 100kb ram (including cache and battery backup ram) z programmable operating clock using pll (division ratio: 1/1 to 1/16, multiplication rate: 1 to 16) z hardware multimedia accelerator (64-bit internal processing) z multifunctional calculation module (multiply and accumulation, matrix, and vector computations) z i2s audio interface with one i nput and one output channel (supports 24-bit format) z 16-ch. dma controller (triggered with peripheral circuits) z local bus interface for external lsi (8/16-bit data bus) z sdram controller with burst control z abundant serial inter faces (uart 2ch., fsio (serial i/f with fifo, supports irda1.0) 2ch., efsio(ext ended serial i/f with fifo, supports iso7816 mode/irda1.0) 2ch., spi 4c h., dcsio (i 2c bus master i/f emulator) 4ch.) z 4ch. of 16-bit pwm control time rs with igbt control function z 4ch. of 8-bit programmable timers z nand flash inter face z infrared remote controller descriptions the S1C33A01 is a high performance 32-bit controller with vari ous serial interfaces, i2s i/o interface, mmc controller and infrared remote controller. it is suitable for multimedia in terface controllers such as audio and various i/o equipment. the S1C33A01 provides an i2s interface t hat has bidirectional i/o channels, this a llows recording and external audio input as well as audio and voice outputs. also it has a hardware arithmetic accele rator to lighten the load on multimedia processing such as audio decoding. an audio player system can be implemented using t he accelerator with the i2s interface. the infrared remote controller, input ports and the serial interf aces are used to easily implement various user interfaces. the S1C33A01 supports reading/writing data fr om/to large capacity storage media such as various card media and flash memory through the built-in mmc controller, spi interface and slc/mlc nand flash interface. furthermore, the local bus interface for an external lsi allows connection of an ex ternal lsi such as an lcd controller and usb controller to expand the functions. the S1C33A01 is equipped with the 32-bit risc cpu core c33, 2kb instruction/data caches, 100kb ram, dma controller, memory controller (sram/s dram), various timers, real-time clock and general-purpose i/o ports as its basic functions, so it can also be used as a high per formance general-purpose cpu. these S1C33A01 functions are impl emented by epson soc (system on chip) design technology using 0.18 m multi-vth. cmos process. ? features z technology ? 0.18 m al-4-layers multi-vth. cmos process technology z cpu ? seiko epson original 32-bit risc cpu core c33 pe with amba bus, optimized for soc ? maximum operating frequency: 90 mhz ? internal 2-stage pipeline ? instruction set: 125 instru ctions (16-bit fixed length) ? cache: 1kb instruction cache and 1kb data cache ? memory space - up to 4gb accessible (32-bit address) z internal memories (ram) ? 16kb iram 1 used as a general- purpose ram. 2kb are used as cache. ? 64kb iram 2 used as a general-purpose ram. ? 16kb iram 3 used as a general-purpose ram. ? 2kb dst ram used as a general-purpos e ram or a dma descriptor table ram. ? 2kb bbram data can be held by a power supply separated with the system power. z operating clock ? main clock - 100 mhz (max.) (tbd)
S1C33A01 2 seiko epson corporation - on-chip oscillator (crystal or ceramic) or external clock input - pll: integer multiplication pll circuit ? sub clock - 32.768khz(typ.) for rtc or low-speed (low power) operation - on-chip oscillator (crystal z mini cache controller (mini cache) ? 1kb instruction cache and 1kb data cache with 4-way associative frame architecture ? lru replacement algorithm ? automatic lock function in debug mode or interrupt handling with specified priority ? write through function with 1-word write buffer * cache memory is shared with iram1. z multimedia accelerator ? hardware continuous multiply and accumu lation circuit (64-bit internal processing) ? supports signed/unsigned integer ar ithmetic operations and fi xed-point arithmetic oper ations with saturation processing. z universal dma controller (udma) ? 2 channels of fast-udm a and 14 channels of table-udma ? dual-address transfer (source and destination addresses are specified) ? supports single or successive transfer. ? high performance burst transfe r function through sdram controller ? 1-byte, 1-halfword, 1-word, 4-byte, 4- halfword or 4-word burst transfer programmable ? built-in dma trigger system with a linkage function ? software or hardware triggers are selectable. z sram controller (sramc) ? provides up to 8 chip enable signals to connect external devices. ? flash rom, sram, or assp (l cd driver) devices can be connected. ? 24-bit address bus and 8/16-bit selectable data bus ? programmable bus access wait cycles (1 to 16 cycles) ? supports little endian access. ? memory mapped i/o ? a memory area (area 6) is reserved for on-chip resources use. ? supports both a0 and bs (bus strobe) access types. ? supports external wait requests using the #wait pin. z sdram controller (sdramc) ? 16-bit sdram interface up to 90 mhz clock rate (tbd) ? supports 16m-bit (2mb) to 512m-bit (64mb) sdram. ? embedded iqb (instruction queue buffer) and dqb (data queue buffer) (mini-cache must be disabled.) ? optimized multi-master access request to minimize average read latency ? programmable cas latency, 1, 2 and 3 ? supports burst transfer. ? sync. clock is configurable into the same or double cpu clock frequency. ? incorporates a 12-bit auto-refresh counter. ? intelligent self-refresh function for low power operation z multifunctional calculation module (calculation module) ? vector computations (additi on, subtraction and multiplication) ? multiply and accumulation (mac) ? matrix computation (2 ? 2, 3 ? 3, 4 ? 4) ? affine transformation (3 ? 3 + 3) ? butterfly computation ? supports signed/unsigned 32-bit int eger operation mode and 32-bit fixed-point values operation mode with saturation processing. z i2s audio interface (i2s) ? supports universal audio i 2 s bus interface. ? i 2 s bus interface with 1 input channel and 1 output channel ? supports up to 24-bit data format. ? dac device clock, word clock and bit clock can be controlled in output channel (e xternal clock can be used). ? provides fifo (24 bits ? 2 channels ? 4) individually for input and output channels. ? supports dma transfer. *an external dac and/or adc are required to output an audio signal to speakers/ear phone and/or to input sound from a microphone. z local bus for external lsi ? an 8/16-bit local bus to connect a graphics lsi or a usb lsi. ? maximum 8mb or 16mb local bus address space (up to 24 address signals are available.) ? external wait requests input to the #lwait/#lready pin are acceptable. ? supports single address mode dma. z clock management unit (cmu)
S1C33A01 seiko epson corporation 3 ? selects the system clock source (osc3, pll or osc1). ? controls the osc3 and osc1 oscillator circuits. ? controls the clock division ratio (1/1 to 1/16) and pll frequency multiplication rate ( ? 1 to ? 16). ? controls clocks in standby mode (sleep and halt). ? controls division ratios of the internal core and peripheral clocks. controls external bus clock. z interrupt controller (itc) ? controls 16 channels of interrupts reserved for c33 pe core. ? supports 48 channels of interrupt sources (some of them are reserved). z watchdog timer (wdt) ? 30-bit watchdog timer that generates a nmi (non-maskable interrupt) or reset ? the watchdog timer overflow period (nm i/reset generation cycle) can be programmed. ? the watchdog timer overflow signal can be output to external devices. z 16-bit timers (t16) ? 4 channels of 16-bit timer/c ounters with pwm control function ? a digital dac function is implemented using the pwm output and an external rc filter. ? 4 channels of built-in output comp arators can be used for controlling igbt. z 8-bit timers (t8) ? 4 channels of 8-bit programmable timer/counters * two channels are reserved as the baud-rate counters for the serial interface (uart). z serial interface (uart, fsio, efsio) ? uart - 2 channels of uart - supports irda 1.0 interface - contains 2-byte receive data buffer and 1-byte tr ansmit data buffer to support full-duplex communication. - transfer rate: 150 to 115200 bps - data length: 7 or 8 bits - parity mode: even, odd or no parity - stop bit: 1 or 2 bits - parity error, framing error and overrun error are detectable. - supports dma transfer. ? fsio (serial interface with fifo) - 2 channels of clock synchronous/asynchronous serial interface - contains fifo (4-byte receive data buffer and 2-by te transmit data buffer are available for each channel). - contains an irda1.0 interface. - contains a baud-rate generator (12-bit programmable timer). - supports dma transfer. ? efsio (extended serial interface with fifo) - 2 channels of clock synchronous/asynchronous serial interface - contains fifo (4-byte receive data buffer and 2-by te transmit data buffer are available for each channel). - contains an irda1.0 interface. - contains a baud-rate generator (12-bit programmable timer). - supports iso7816 mode (ch.1 only). alternative msb or lsb memory card interface compatible with iso7816-3 t=0 & t=1 protocol programmable baud-rate and guard-time generation iso7816 acknowledge and autom atically repeat transmission - supports dma transfer. z spi (serial peripheral interface) ? 4 channels of spi ? supports both master and slave modes. ? data length: 1 to 8 bits ? can be operated with up to a half of the system clock frequency. ? supports dma transfer. z dcsio (i 2 c master emulator) ? 4 channels of i/o ports with a serial shifter ? emulates i 2 c master device. ? input/output level detec tor to drive state machine ? emulates 1-wire or 2-wire communication protocol by software. ? supports dma transfer. z real time clock (rtc) ? contains time counters (second, minute, and hour) and calendar counters (day , day of the week, month, and year). ? bcd data can be read/wr itten from/to the counters. ? 24-hour or 12-hour mode can be selected. ? operates with the power source (rtcv dd = 1.8 v typ.) separated from the system power supply (lv dd ). ? the wakeup output pin and #stby input pi n are provided for chip standby/wakeup control. z general-purpose i/o port control (gpio) ? controls up to 96 (qfp20-184pin, pf bga12u-180) or 64 (tqfp24-144pin) i/o ports.
S1C33A01 4 seiko epson corporation ? built-in pull-up resistors can be cont rolled by software (except some ports). the i/o ports are shared with other peripheral function pi ns (for interfaces and timers). therefore, the number of i/o ports depends on the per ipheral functions used. z slc/mlc nand flash interface with reed-solomon ecc (card) ? 8-bit slc/mlc nand flash can be controlled. ? hardware reed-solomon ecc calculation for slc/mlc nand flash the hardware reed-solomon ecc calcul ation function supports error detection only. ? provides smartmedia i/f signals (#smre and #smwe can be generated). ? supports nand flash booting function. z infrared remote controller (remc) ? infrared remote controller wi th 1 input channel and 1 output channel ? duty and pulse width can be configured in bit units (supports various logical formats by software control). an external infrared detecting unit is requi red to receive infrared remote control signals. z operating voltage ? core voltage (lv dd ): 1.65 to 1.95 v (1.80 v typ.) ? i/o voltage (hv dd ): 2.70 to 3.60 v (3.30 v typ.) ? system bus voltage (busv dd ): 2.30 to 3.60 v (3.30 v typ.) ? rtc voltage (rtcv dd ): 1.65 to 1.95 v (1.80 v typ.) ? pll voltage (pllv dd ): 1.65 to 1.95 v (1.80 v typ.) z operating temperatures ? -40 to 85c z power consumption ? during sleep: 1.0 ua (while only rtc is operating (power is supplied only to rtcvdd and not supplied to all others) ? during halt: 3.5 ma (when pll = off, and all clocks are set to 48mhz) ? during execution: 103.5 ma (when pclk = 45mhz, mc lk = sdclk = 90mhz, and the clock is supplied to all peripheral circuites) by controlling the clocks through the clock m anagement unit (cmu), power consumption can be reduced. z shipping form ? pfbga12u-180 (12 mm 12 mm 1.2 mm, 0.8 mm ball-pitch) ? tqfp24-144pin (16 mm 16 mm 1.0 mm, 0.4 mm pin-pitch) ? qfp20-184pin (20 mm 20 mm 1.4 mm, 0.4 mm pin-pitch)
S1C33A01 5 ? block diagram semiconductor operations division ic sales department ic international sales group 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 http://www.epson.jp/device/semicon_e/ epson semiconductor website document code: 411213901 first issue april, 2008 l revised dec, 2009 in japan notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ? seiko epson corporation 2009, all rights reserved S1C33A01 c33pe core minicache calculation module udma local bus interface pll cmu itc i 2 s memc reg. udma reg. timer (t 16/t8) sio (uart/sif/efsio) spi dcsio card remc wd t gpio misc rt c sd ramc sr am c memory controlle r (memc) bo ot se quen cer bb ram arbiter iram-1 (16kb) exter nal lsi rt cv dd external memory dstram (2kb) iram-2 (64kb) iram-3 (16kb) a3ram arbiter bbr am (2kb) mu ltime dia accele ra tor S1C33A01 c33pe core minicache calculation module udma local bus interface pll cmu itc i 2 s memc reg. udma reg. timer (t 16/t8) sio (uart/sif/efsio) spi dcsio card remc wd t gpio misc rt c sd ramc sr am c memory controlle r (memc) bo ot se quen cer bb ram arbiter iram-1 (16kb) exter nal lsi rt cv dd external memory dstram (2kb) iram-2 (64kb) iram-3 (16kb) a3ram arbiter bbr am (2kb) mu ltime dia accele ra tor
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